7 s emiconductor , i nc. fea tures ? 5v operation ? full duplex asynchronous receiver and transmitter ? easily interfaces to most popular micro- processors ? adds or deletes standard asynchronous communication bits (start, stop, and parity) to or from a serial data stream ? independently controlled transmitter , receiver , line status, and data set interrupts ? programmable baud rate generator allows division of any input clock by 1 to (2 16 -1) and generates the internal 16 x clock ? independent receiver clock input ? modem control functions (cts, r ts, dsr, dtr, ri,and dcd) ? fully programmable serial interface characteristics: - 5, 6, 7, or 8 bit characters - even, odd, or no-parity bit generation and detection - 1, 1.5, or 2 stop bit generation - baud generation (dc to 56k baud) ? false start bit detection ? complete status reporting capabilities EI16C550 fifo u ar t pin configura tion ? t ri-state ? ttl drive capabilities for bi- directional data bus and control bus ? line break generation and detection ? internal diagnostic capabilities: - loopback controls for communications link fault isolation - break, parity overrun, and framing error simulation ? fully prioritized interrupt systems controls ? 16 byte fifo for reduced cpu overhead description the epic EI16C550 universal asynchronous receiver t ransmitter (uar t) is a cmos-vlsi communication device in a single package. the uar t performs serial to parallel conversion on data characters received from a p eriph e ral device or a modem, and parallel-to-serial conversions on data charac- ters received from the cpu. the cpu can read the complete status of the uar t at any time during the functional operation. status information reported includes the type and condition of the transfer operation being performed by the uar t , as well as any error conditions (party , overrun, framing, or break detect). 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 e i 1 6 c 5 5 0 d0 d1 d2 d3 d4 d5 d6 d7 rclk sin sout cs0 cs1 cs2 ? baudout ? xt al1 xt al2 dostr ? vss vcc ri ? dcd ? dsr ? cts ? mr out1 ? dtr ? r ts ? out2 ? intrpt rxrdy ? a0 a1 a2 ads ? txrdy ? ddis distr distr ? 39 38 37 36 35 34 33 32 31 30 29 7 8 9 10 11 12 13 14 15 16 17 d5 d6 d7 rclk sin nc sout cs0 cs1 cs2 ? baud- out ? mr out1 ? dtr ? r ts ? out2 ? nc intrpt rxrdy ? a0 a1 a2 xt al1 xt al2 dostr ? dostr vss nc distr ? distr ddis txrdy ? ads ? d4 d3 d2 d1 d0 nc vcc ri ? dcd ? dsr ? cts ? 18 19 20 21 22 23 24 25 26 27 28 6 5 4 3 2 1 44 43 42 41 40 EI16C550 40-pin dip 44-pin plcc 36 n.c. 35 reset 34 op1 ? 33 dtr ? 32 r ts ? 31 op2 ? 30 int 29 rxrdy ? 28 a0 27 a1 26 a2 25 n.c. n.c. 1 d5 2 d6 3 d7 4 rclk 5 n.c. 6 rx 7 tx 8 cs0 9 cs1 10 cs2 ? 1 1 baudout ? 12 48 n.c. 47 d4 46 d3 45 d2 44 d1 43 d0 42 vcc 41 ri ? 40 cd ? 39 dsr ? 38 cts ? 37 n.c. n.c. 13 xt al1 14 xt al2 15 -iow 16 iow 17 gnd 18 ior ? 19 ior 20 n.c. 21 ddis ? 22 txrdy ? 23 as 24 48-pin tqfp EI16C550
semiconductor, inc. 8 EI16C550 fifo uart the uart includes a programmable baud generator which is capable of dividing the timing reference clock input by divisors of 1 to (2 16 -1) , and producing a 16 x clock to drive the receiver logic. also included in the uart is a complete modem control capability, and processor interrupt system that may be software tai- lored to the users requirement to minimize the com- puting needed to handle the communications link. (15) baudout receiver buffer register line control register divisor latch (ls) divisor latch (ms line status register fifo modem control register modem status register interrupt enable register interrupt id register data bus buffer receiver shift register receiver timing & control transmitter timing & control transmitter shift register modem control logic baud generator interrupt control logic select and control logic d7-d0 (1-8) (28) (27) (26) (12) (13) (14) (25) (35) (22) (21) (19) (18) (23) (24) (16) (17) (29) a0 a1 a2 cs0 cs1 cs2? adr mr distr distr? dostr dostr? ddis txrdy? xtal1 xtal2 rxrdy? power (40) 3.3, 5v supply (20) gnd intrpt (30) (32) rts? (36) cts? (33) dtr? (37) dsr? (38) dcd? (39) ri ? (34) out1? (31) out2? sout (11) (9) rclk (10) sin fifo control register internal data bus block diagram
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